Field effect transistors (“FET”) have completely replaced bipolar transistors, becoming the solid-state components most widely used in the production of integrated circuits (IC). FET transistors can in fact be provided with much smaller dimensions than bipolar transistors (BJT) and their production process is relatively simple. Further, the power consumption is lower than that of BJTs, especially at low frequencies.
The FET family comprises many mutually different devices. These devices can be divided mainly into three categories:                Floating-gate MOSFETs (FGMOS—Floating Gate MOS);        Bulk MOSFETs;        SOI (Semiconductor On Insulator) MOSFETs.        
The first are MOSFETs used in the production of nonvolatile memories, which are characterized by the property of being able to retain the stored information even in the absence of power supply voltages. Examples of memories which use FGMOSs are EPROMs, EEPROMs and Flash (with ETOX cell).
The second MOSFETs, also known as “conventional” (FIG. 1a), are the most widespread field effect transistors in the production of logic circuits and volatile memories such as SRAMs (Static Random Access Memory) and DRAMs (Dynamic RAM). This category includes enhancement MOSFETs and depletion MOSFETs, in which the device is built inside a semiconductor substrate and insulated from the others by means of inverse junctions.
Finally, SOI technology, is the latest evolution of the CMOS and consists in fabricating the MOS transistor in an insulating substrate (generally silicon oxide) known as BOX (Buried OXide).
There are several SOI structures. Among them, the fundamental ones are the “partially depleted” or PD SOI (FIG. 1b) and the “fully depleted” or FD SOI (FIG. 1c). Besides these devices, SOI technology allows to fabricate even more advanced configurations, such as double- and triple-gate devices.
As is known, when the voltage VGS between the gate and the source is higher than the threshold voltage Vt and a voltage VDS>0 is applied between drain and source, a current IDS flows from the drain to the source. If the VDS is low, this current can be expressed as:
      I    DS    =            μ      n        ⁢          C      ox        ⁢                  W        L            [                                    (                                          V                GS                            -                              V                t                                      )                    ⁢                      V            DS                          -                              V            DS            2                    2                    ]      where: μn is the average mobility of the electrons in the channel;
Cox is the capacitance per unit area of the gate oxide;
W is the width of the MOSFET;
L is the length of the channel;
and Vt is the threshold voltage.
For VDS=VGS−Vt=VDSsat (Saturation voltage), one has VGD=Vt and therefore the channel formed in the substrate at the interface with the gate oxide is pinched at the drain end (the phenomenon of pinch-off).
In these conditions, a more correct formula for IDSsat, which takes into account this last remark as well, is the following:
      I    DSsat    =            1      2        ⁢          μ      n        ⁢          C      ox        ⁢          W      L        ⁢                  (                              V            GS                    -                      V            T                          )            2        ⁢          (              1        +                  λ          ⁢                                          ⁢                      V            DS                              )      where λ is a technological parameter, which depends on the fact that as VDS above VDSsat, the pinch-off point shifts toward the source, reducing the actual channel length, reducing channel resistance and thus increasing IDSsat (an effect known as “channel length modulation”).
In a bulk MOSFET, the threshold voltage depends on the bias of the substrate (“body” effect). As is known, the dependency of Vt on the voltage between the substrate (“body”) and the source VBS leads to a decrease of IDS, VDSsat and IDSsat, which become respectively:
            I      DS        =                  μ        n            ⁢              C        ox            ⁢              W        L            ⁢              n        [                                                            (                                                      V                    GS                                    -                                      V                    t                                                  )                            n                        ⁢                          V              DS                                -                                    V              DS              2                        2                          ]                        V      DSsat        =                            V          GS                -                  V          t                    n                                                I            DSsat                    =                                    I              DS                        ⁢                          |                                                V                  DS                                =                                  V                  DSsat                                                      ⁢                          (                              1                +                                  λ                  ⁢                                                                          ⁢                                      V                    DS                                                              )                                                                    =                                    1              2                        ⁢                          μ              n                        ⁢                          C              ox                        ⁢                          W              L                        ⁢                          1              n                        ⁢                                          (                                                      V                    GS                                    -                                      V                    t                                                  )                            2                        ⁢                          (                              1                +                                  λ                  ⁢                                                                          ⁢                                      V                    DS                                                              )                                          
In order to model correctly current MOS devices, which are characterized by a short channel, i.e., shorter than 10 μm, it is not possible to resort to formulas for long channels such as the ones discussed above, but it is necessary to consider other secondary physical aspects, such as for example mobility degradation and velocity saturation.
As the electrons that constitute the drain current cross the channel, they are in fact deflected by the collisions they undergo when they encounter the surface or the acceptor atoms of the non-inverted substrate or when they collide with the thermal phonons generated by the vibrations of the lattice. Accordingly, the mobility of the carriers in the channel decreases as the transverse electrical field increases (mobility degradation) and their velocity, for high values of the longitudinal electrical field Ey, tends to settle at a limit value νsat known as “saturation velocity”.
Therefore, the expressions cited above must be corrected so as to take into account the effective mobility of the carriers in the channel, which as is known is:
      μ    eff    =            μ      0              1      +                        (                                    E              eff                        /                          E              0                                )                v            where μ0, E0 and ν are all fitting parameters and Eeff is the average electrical field in the direction “x” which lies transversely to the channel, also known as “effective electrical field”, which affects the free channel electrons. Eeff is:
      E    eff    ≅            1              3        ⁢                                  ⁢                  t          ox                      ⁢          (                                                  V              GS                        +                          V              t                                2                -                  V          FB                -                              2            /                          ϕ              p                                /                    )      where tox is the thickness of the gate oxide, VFB the so-called “flat-band voltage” and |φp| is the modulus of the potential of an electron in the p-type semiconductor.
In the SOI-PD MOSFET (FIG. 1b), the thickness of the layer of source silicon (tSt) is greater than the maximum extension of the space charge region (xd max).
Accordingly, below the depletion region there is always a neutral region which shields electrostatically the channel from the back-gate electrode (BG), i.e., from the substrate that lies below the BOX. Therefore, in the SOI-PD the threshold voltage does not depend on the back-gate potential. Moreover, the presence of the BOX makes the source-body and drain-body junction capacitances negligible.
The behavior of a SOI-PD is similar to the behavior of a conventional bulk MOSFET, but differently from said bulk MOSFET, since there is no body contact, it is affected by some additional parasitic effects known as “Floating Body Effects” (FBE). To eliminate these unwanted effects, it is possible to provide a body contact, obtaining a so-called “Body-Tied SOI” (BT SOI) MOS, which as is known can be provided with a single contact, double contact or multiple symmetrical contact.
If the substrate of a BT SOI transistor, instead of being permanently connected to the ground (nMOS) or to VDD (pMOS), is short-circuited with the gate, the device is known as “Dynamic Threshold MOSFET” (DT MOS). In this device, if VGS=VBS increases, the threshold voltage decreases and therefore the channel current Ich increases. Further, since the body-source voltage VBS is equal to the collector-emitter voltage VCE the parasitic BJT formed by the source, body and drain, as the body potential increases, so does the collector current IC. The combined effect of these two phenomena causes, therefore, a rapid increase in the total drain current.
Differently from the SOI PD MOSFETs discussed above, in Fully Depleted or FD SOI transistors (FIG. 1c) the thickness of the source silicon layer (tSi) is lower than the maximum extension of the space charge region that is present in the substrate (xd max).
Accordingly, in these devices the substrate is fully depleted for VGS=Vt, independently of the bias applied to the back gate (except for a fine accumulation or inversion layer which can occur at the lower BOX/substrate interface, when the back-gate is biased by a high positive or negative voltage).
Fully Depleted SOIs, due to the absence of any neutral region in the substrate, are not affected by the floating body effects (at least as regards functional situations in which both front-gate and back-gate control electrodes have positive or no bias). Only three types of these particular MOSFETs are known: (i) the Single Gate SOI FD MOSFET (SG-MOS), in which tBOX>>tox and the body, which acts as a mechanical support, is held to the ground; (ii) the Ground Plane SOI FD MOSFET (GP-MOS), where tBOX>tox and the back-gate is used to adjust the threshold voltage VT; (iii) the Double Gate MOSFET (DG-MOS), where tBOX=tox and the two gates (FG and BG) are short-circuited.
Although, as shown, the evolution of MOS technology has led to devices which are increasingly less affected by secondary and parasitic phenomena, the corresponding applications are still limited by the inherent unidirectional nature of the operation of MOS transistors, which entails forced design choices in the integrated circuit.
This limitation also affects the number of transistors required to perform a certain function in integrated circuits, in particular in memories and in logic or sequential circuits.